MICROELECTRONICS RESEARCH CENTERS SELECTED

The Semiconductor Industry Association (SIA) and the Defense Advanced Research Project Agency (DARPA) have selected two of potentially six microelectronics research centers. The centers will focus on core chip technologies with long term technological payback.

Funding will be provided by SIA (50%), DARPA (25%) and SEMATECH, a consortia of U.S. semiconductor suppliers (25%). Each center, when fully operational, is expected to receive approximately $10 million annually, however, actual funding levels and the number of centers established will depend on the review of these two centers following their first two years of operations. Total funding for the centers could reach $600 million over 10 years.

The concept of the focused centers is to address several areas of concern for U.S. semiconductor manufacturers: reduced semiconductor research funding from all traditional sources, including the Department of Defense and large industrial labs, increased industry emphasis on short-term research — heightened by a industry-funded university research environment not conducive to nurturing longer range projects; and a lack of synergy among disparate university researchers.

The selected centers, funded through 2001, are: 

• Design and Test Focus Center, led by the University of California at Berkeley and including Stanford, Princeton, MIT, Michigan, UCLA, UC Santa Barbara, UC San Diego, UC Santa Cruz, and Carnegie Mellon. The center will investigate software programs used to design chips and semiconductor component testing.

• Interconnect Focus Center, led by Georgia Tech and including MIT, Stanford, Cornell, Rensselaer Polytechnic Institute, and the State University of New York at Albany. The center will conduct research on wiring that connects millions of transistors on a microchip.

The technological foci for these and future centers were identified in the National Technology Roadmap for Semiconductors, which outlines long-term critical technological barriers for the semiconductor industry. Separate solicitations for the Interconnect and Design/Test centers were offered by DARPA; proposal review and funding recommendations were made jointly by industry and DARPA program managers.

Technological barriers identified in the National Technology Roadmap for Semiconductors that could serve as research focus for future centers include lithography, front end processes, factory integration, assembly/packaging, and process integration, devices and structures. The 1999 review and rewrite of the Roadmap will likely revise the list. If the first two centers are found beneficial, the next round of proposals is to occur in the year 2000.

More information can be obtained by contacting Dan Radack at DARPA at 703/696-2216 or on the Web at http://marco.fcrp.org/